The present invention relates to interconnection structures for computing and communication systems. More specifically, the present invention relates to a scaleable low-latency switch for usage in a multiple level interconnection structure.
A persistent and significant unsolved problem in the field of computer science and communications has been the lack of a scaleable, low-latency interconnect that sustains high throughput, a high cross-sectional bandwidth, under fully loaded conditions. Existing interconnect designs, such as banyon, omega and fat-tree networks, multi-level grids, torus and hypercube networks, all fail in various degrees to scale without limit, and to support low latency and high throughput when loaded with traffic. Geometries of existing networks were developed by Nineteenth Century mathematicians, and even earlier geometricians, and were never intended to support a message-routing method.
What is needed is an interconnect structure and a suitable switch for use in forming interconnections in the structure that are scaleable virtually without limit, and that support low latency and high throughput.
What have been discovered are a family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, LAN switches, IP and ATM switches, telephony central office switching, video on demand servers, interconnects for mainframe database servers, high-speed workstation interconnects, and many others that are known to those having ordinary skill in the art.